(1) Field of the Invention
The present invention relates to liquid crystal display panels. More particularly, the present invention relates to thin film transistors (TFTs) and a method for making thin film transistors having a gate electrode and gate line electrodes connected by means of a metal line in a thin film transistor formed of polysilicon.
(2) Description of the Prior Art
As contemporary image display devices, such as high definition television sets, have been developed, flat panel display devices have been much in demand. The liquid crystal display is representative of techniques used to make flat panel display devices. The liquid crystal display (LCD) contributes a combination of colorgenic features, low power consumption, and high speed performance that electroluminescence devices (EL), vacuum fluorescence displays (VFD), plasma display panels (PDP), etc., have failed to attain.
An LCD device may be characterized as an active device, or a passive device. The active device is superior to the passive device in performance speed, and in view angle and contrast readability. Thus, the active LCD device has been identified as being the most appropriate display device for high definition television sets which require resolution of more than one million pixels. As the importance of thin film transistors has been recognized in future commercial products, research activities directed TFTs have increased.
Research in the field of thin film transistors, which serve as electrical switches for selective driving of pixel electrodes in the liquid crystal display devices, has focused on improvements in the structure of the transistors, in the performance characteristics of the amorphous or polycrystalline silicon, and in the prevention of ohmic contact failures, opens and shorts, in the TFT electrodes. Each of these improvements ultimately enhances production yield.
Polycrystalline silicon thin film transistors are favorite elements used to form switching devices and peripheral driving circuits in liquid crystal display panels. Accordingly, a great deal of research has recently been devoted to thin film transistors for large scale LCDs which can be mass produced at low cost.
The most common materials used to form the substrate in a liquid crystal display panel is transparent glass produced in a low temperature fabrication process, and quartz produced in a high temperature fabrication process.
The steps of a conventional method used to manufacture a thin film transistor in a liquid crystal display panel are illustrated in FIGS. 1A to FIGS. 1F.
As shown in FIG. 1A, the formation of a conventional thin film transistor begins with depositing a silicon layer 12 on a transparent substrate 10. The silicon layer 12 is patterned, and an insulating layer 14 is deposited to overlay the upper surface of silicon pattern 12 and to surround both sides of silicon pattern 12, as shown in FIG. 1B.
Insulating layer 14, typically an oxide layer, may be grown in an ambient atmosphere of oxygen, or may be grown by a chemical vapor deposition.
Subsequently, a polycrystalline silicon layer 16 is deposited over the surface of substrate 10 on which the silicon pattern 12 is formed, as shown in FIG. 1C, and silicon layer 12 is doped by means of POCL.sub.3 to lower it ohmic resistance. Subsequently, as shown in FIG. 1D, a gate pattern 16 is formed from the polycrystalline silicon layer, and ion implantation is performed.
As a result, ion implantation to form active drain/source regions is made into the entire upper surface of the resulting structure, except the region underlying gate electrode 16. An isolation oxide layer 18 is then deposited over the upper surface of the substrate on which the pattern is formed as shown in FIG. 1E. In order to achieve subsequent planarization of this layer, a borophosphosilicate glass (BPSG) may be used.
Activation of the implanted ions is carried out at a temperature of more than 800.degree. C. After that, contact holes are selectively formed through isolation oxide layer 18, as shown in FIG. 1F, and a metal layer 20 is deposited to a predetermined thickness over and adjacent to the contact holes to form the source/drain electrodes, whereby the formation of a polycrystalline silicon, thin film transistor is completed. In order to reduce off current, the foregoing structure having light doped drain (LDD) may be used.
FIG. 2 depicts a top plan view of the conventional thin film transistor for use in a liquid crystal display device. Reference numerals designate the following parts: 12 a silicon pattern; 22 a contact; 23 a gate. A sectional view of the gate taken along lines A-A' has a structure appearing in FIG. 1C.
In a case where the cross-sectional view of the gate has the structure shown in FIG. 1C, a "weak point," exists within this structure, as denoted by II in FIG. 1C, which increases leakage current and degrades overall reliability of the TFT.
A 1991 article in the Journal of Electrochemical Society, Issue 138, page 802 by Troxel et al. entitled Enhanced Polysilicon Thin-Film Transistor Performance by Oxide Encapsulation, discloses the structure of the weak point. FIGS. 3A through 3C illustrate the teachings of this article. In FIG. 3A, a silicon layer 12 is deposited over a transparent substrate 10, and an oxide layer 14 of SiO.sub.2 and a silicon nitride layer 17 are serially deposited over silicon layer 12. The oxide layer and silicon nitride layer are patterned into islands by means of a photoresist pattern.
The photoresist pattern is removed and thermally oxidized to form the oxide layer 14 shown in FIG. 3B. After the oxide layer 14 has been formed, the silicon nitride layer is removed. A gate layer 16 is deposited on the pattern of FIG. 3B to remove the weak point appearing in the conventional TFT.
U.S. Pat. No. 5,120,667 discloses a technique for forming a TFT having reduced leakage current and a simplified fabrication process. This technique is illustrated in FIGS. 4A to 4D.
To explain the above fabrication process briefly, a silicon layer 12, a thermal oxide layer 14 (or an oxide layer) and a gate polysilicon layer 16 overlay one another on a transparent substrate 10. The gate polysilicon layer 16 is doped and patterned into islands so as to form the structure shown in FIG. 4A. The insulating layer 19 is applied to the resulting substrate, as shown in FIG. 4B.
After that, the insulating layer 19 is etched by a reactive ion etching to reduce the insulating layer 19 to twin side walls covering both sides of oxide layer 14, as shown in FIG. 4C. A polysilicon layer 21 is deposited over the resulting substrate to yield the structure of FIG. 4D.
According to the above fabrication process, a silicon pattern is formed then patterned, an oxide layer is deposited, and an insulating layer is formed into side walls in order to prevent the side edges of the patterned silicon from being exposed.